*UPDATE* this is from the wrong file - it's from the 64MB, 480x272 pixel version of the A330?
I'll check out the other file when I get home.
Hmmmm good tip. Here's some interesting stuff from /ucosii/jz4740/nandboot/virgo.h
#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 /* NAND Boot config code */
#define CFG_NAND_UCOS_OFFS (256 * 1024)
#define CFG_NAND_UCOS_START (0x80100000)
#define CFG_NAND_UCOS_DST (0x80100000)
#define CFG_NAND_UCOS_SIZE ( 2 * 1024 *1024)
//#define CFG_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
#define CFG_CPU_SPEED 144000000 /* CPU clock: 336 MHz */
#define CFG_EXTAL 12000000 /* EXTAL freq: 12 MHz */
Looking at jz4740.h, has some interesting definitions. Obviously the registers are areas to avoid:
//----------------------------------------------------------------------
// Register Definitions
//
#define CPM_BASE 0xB0000000
#define INTC_BASE 0xB0001000
#define TCU_BASE 0xB0002000
#define WDT_BASE 0xB0002000
#define RTC_BASE 0xB0003000
#define GPIO_BASE 0xB0010000
#define AIC_BASE 0xB0020000
#define ICDC_BASE 0xB0020000
#define MSC_BASE 0xB0021000
#define UART0_BASE 0xB0030000
#define I2C_BASE 0xB0042000
#define SSI_BASE 0xB0043000
#define SADC_BASE 0xB0070000
#define EMC_BASE 0xB3010000
#define DMAC_BASE 0xB3020000
#define UHC_BASE 0xB3030000
#define UDC_BASE 0xB3040000
#define LCD_BASE 0xB3050000
#define SLCD_BASE 0xB3050000
#define CIM_BASE 0xB3060000
#define ETH_BASE 0xB3100000
So there's possible free RAM after the ucos kernel:
start addr x80100000 + size of 0x00200000
finish addr 0x802FFFFF
So perhaps there is space between 0x80300000 and 0x80A00000. About 7MB of RAM. Would be very useful.
There maybe be bits and pieces of RAM used by the kernel in here but I bet there's some nice big chunks that could be used?