Author Topic: More available memory under native firmware  (Read 2799 times)

slaanesh (OP)

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    • Slaanesh Dev
More available memory under native firmware
« on: February 28, 2013, 11:06:32 am »
The Dingoo A320 has 32MB. Its seems like 16MB is user available by the native firmware.
That means 16MB is not and taken by the system.

This really seems like a hefty chunk.

My gut feeling is that there are big fat buffers for things like video, mp3s... buffers that can be used for storing bigger ROMs for MAME4ALL.

Has anyone had a look at the A320 memory map?

Is there anything documentation regarding the A320 memory map?
Seems like the usable space is from:

Programs start at: 0x80a00000
In a sample run of mallocs the address ranged from 0x8113201c to 0x81fe9aa8 or about 15.4MB of heap.
That was with a program sized just under 1MB.


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Re: More available memory under native firmware
« Reply #1 on: February 28, 2013, 11:51:17 am »
You could look at ucosii sources and see why it has such a strange memory layout. - This one is ingenic version for jz4740 soc and doesn't contain dingoo specific code but the memory handling part should be identical.

PS: Shame that ucos doesn't have mmap() and virtual memory.
GCW-Zero prototype, Dingoo a320, Ritmix rzx-50, Dingoo a380, Xperia Play

slaanesh (OP)

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    • Slaanesh Dev
Re: More available memory under native firmware
« Reply #2 on: March 01, 2013, 12:08:44 am »
*UPDATE* this is from the wrong file - it's from the 64MB, 480x272 pixel version of the A330?
I'll check out the other file when I get home.

Hmmmm good tip. Here's some interesting stuff from /ucosii/jz4740/nandboot/virgo.h

Code: [Select]
#define JZ4740_NANDBOOT_CFG     JZ4740_NANDBOOT_B8R3    /* NAND Boot config code */

#define CFG_NAND_UCOS_OFFS   (256 * 1024)
#define CFG_NAND_UCOS_START  (0x80100000)
#define CFG_NAND_UCOS_DST    (0x80100000)
#define CFG_NAND_UCOS_SIZE   ( 2 * 1024 *1024)

//#define CFG_CPU_SPEED         336000000       /* CPU clock: 336 MHz */
#define CFG_CPU_SPEED           144000000       /* CPU clock: 336 MHz */
#define CFG_EXTAL               12000000        /* EXTAL freq: 12 MHz */

Looking at jz4740.h, has some interesting definitions. Obviously the registers are areas to avoid:

Code: [Select]
// Register Definitions
#define CPM_BASE        0xB0000000
#define INTC_BASE       0xB0001000
#define TCU_BASE        0xB0002000
#define WDT_BASE        0xB0002000
#define RTC_BASE        0xB0003000
#define GPIO_BASE       0xB0010000
#define AIC_BASE        0xB0020000
#define ICDC_BASE       0xB0020000
#define MSC_BASE        0xB0021000
#define UART0_BASE      0xB0030000
#define I2C_BASE        0xB0042000
#define SSI_BASE        0xB0043000
#define SADC_BASE       0xB0070000
#define EMC_BASE        0xB3010000
#define DMAC_BASE       0xB3020000
#define UHC_BASE        0xB3030000
#define UDC_BASE        0xB3040000
#define LCD_BASE        0xB3050000
#define SLCD_BASE       0xB3050000
#define CIM_BASE        0xB3060000
#define ETH_BASE        0xB3100000

So there's possible free RAM after the ucos kernel:
start addr x80100000 + size of 0x00200000
finish addr 0x802FFFFF

So perhaps there is space between 0x80300000 and 0x80A00000. About 7MB of RAM. Would be very useful.

There maybe be bits and pieces of RAM used by the kernel in here but I bet there's some nice big chunks that could be used?

« Last Edit: March 01, 2013, 01:14:32 am by slaanesh »